Pre Silicon Functional Verification Using SV-UVM methodology

In this class, the latest verification techniques for pre-silicon (RTL) verification will be taught. Indian VLSI companies like Nvidia, Intel, Samsung, ARM, Texas Instruments, NXP semiconductors, Qualcomm, AMD has almost 70% jobs for RTL verification posts only. So after taking this course which is ideal for MTECH(2nd year) and BTECH(4th year) students, you will be able to compete better in interviews for full time or intern jobs than your competitors. What you'll learn: Basics of VLSI flow Need of verification in the life cycle of chip Basic DUT Testbench Skeleton Directed Stimulus Coding Self-Checking Testbench Tasks and Functions for Testbench Reuse SystemVerilog Data Types Useful for Verification Process Control, Synchronization, and Mailbox Basics Driver-Monitor Style Testbench Transaction-Based Verification Basics OOP Basics in SystemVerilog Inheritance and Polymorphism Randomization and Constraints Basic Scoreboard and End-to-End Checking UVM Architecture and File Structure UVM Component/Object Coding and Phases UVM Sequence Item and Sequence Coding UVM Driver Coding Learn the fundamentals of pre-silicon verification and how SystemVerilog and UVM enable efficient design validation before silicon. Understand the UVM testbench structure, including sequences, drivers, monitors, and agents, to build scalable and reusable verification environments. Develop a VIP of APB protocol with the gathered knowledge. The course will be 16 Weeks long (1 hr/week) with practical coding example in edaplayground. The total fees of the course is 20000 Rs if done in 1on1 and 15000 Rs if done in a class of 2 persons.