Pranay Samanta

I am a VLSI engineer with 10 years of experience in functional verification field. I'm a highly reliable person who can always be trusted to come up with a solution of issues very quickly and efficiently. So provide me an issue, I will provide you the bug which is causing the issue in the fastest possible manner.
In my work ethics there is no option for failure but I acknowledge my fair share of mistake and failure and accept as a positive experience.
Debugging is my strength, love and passion. I love finding out bugs from design rapidly and provide the solution to designers - which I feel the most important aspect for verification in modern complex designs due to squeezing of time to market. Quicker the company is able to unveil the product in market, more profitable the company would be than its' competitors - that's why I believe I can be an asset to the company I'm working for.
Now I am looking to share my working experience to students as I am planning to switch into the academic domain.
Specialties:
Rapid and effective Debugging
User friendly coding with indentations and comments
UVM | OVM
APB | AXI | JESD | JTAG | PHY SERDES
IP verification | SS verification | SoC verification | FW verification
RAL and Register verification
System Verilog
Test planning
ECC verification
100% Coverage closure (Functional and Code) - No compromise
GLS zero-delay | GLS with SDF - Bugs are found on GLS too
UPF simulation (little)
Scripting
Sharing the knowledge with colleagues and ever smiling attitude.