Verification Methodologies for BTECH students to VLSI Course in semesters

Module:1 Fundamentals of Verification Introduction to VLSI verification - Types of verification - Functional Verification challenges and solutions – Functional Verification Process - Verification planning – Basic Testbench Functionality – Layered Testbench - Directed Testing – Constrained Random Stimulus – Coverage – Code Coverage and Functional Coverage Module:2 System Verilog Introduction to System Verilog – Literal values-data Types – Arrays – Array methods – Creating new types with typedef – user defined structures – Enumerated types – Packages – operators – expressions – Procedural statements and control flow – Processes in System Verilog – Task and functions – Routine arguments – Returning from a routine – SV scheduling semantics – Developing System Verilog Test environment – Case Study Module:3 OOP based Testbench OOP Terminology - Creating Object - object deallocation - copying objects - static variables - Global variables – Inheritance – Polymorphism – Program – Interface - Stimulus timing - Module interactions (Mailbox, Semaphores) - Connecting together – Developing reusable object based self-checking test environment – Generator – Transactor – Driver - Monitor – Scoreboard – Case Study Module:4 Randomization, Functional Coverage Need for Randomization – Randomization in System Verilog – Constraint Details – Solution Probabilities – Controlling Multiple Constraint Blocks – Valid Constraints – In-line Constraints – Common Randomization Problems - Coverage Types – Anatomy of covergroup – Triggering a covergroup – Data Sampling – Cross Coverage – Coverage options – Developing constraint random verification environment Module:5 Universal Verification Methodology (UVM) Basics System Verilog test environment Vs UVM based test environment - Basics of UVM Transaction Level Communication Protocol - Developing reusable verification components - Developing reusable verification environment – Case Study