Digital Chip Design Flow (turning logic into hardware description into silicon)

Describing hardware What is RTL (Register-Transfer Level)? — describing a circuit as registers and the logic transferring data between them, rather than as individual gates What is an HDL (Hardware Description Language)? — describing hardware structurally/behaviorally instead of drawing schematics Verilog vs. SystemVerilog — Verilog as the original IEEE HDL; SystemVerilog as its superset adding stronger typing, interfaces, and verification constructs Verilog basics: modules (the basic unit of hardware), input/output ports, wire vs. reg / logic (what each represents — a connection vs. a storage/procedural-assignment target) Combinational logic in Verilog — assign statements, continuous assignment Sequential logic in Verilog — always_ff (or always @(posedge clk) ), why sequential logic must be clocked and how this maps back to the D flip-flop from Section 4 From RTL to a real netlist — Synthesis What is synthesis? — the process of translating RTL into a gate-level netlist built from a specific standard cell library PPA (Power, Performance, Area) — the three-way optimization synthesis performs, and why they trade off against each other Why the synthesized netlist looks nothing like the RTL you wrote (technology mapping, optimization, retiming) Verification (arguably the most effort-intensive part of the whole flow) What is a testbench? — the surrounding environment that drives inputs into a design and checks outputs Why verification is one of the most important steps in hardware design — silicon bugs can't be patched after fabrication the way software can What is hardware simulation? — executing the RTL/netlist model against a testbench without real silicon What are waveforms? — the time-domain view of every signal's value, the primary debug tool How to build a simple testbench — instantiate the design under test (DUT), generate a clock, drive stimulus, add checkers/assertions, observe results Types of verification/coverage — functional coverage, code coverage (line/branch/toggle), assertionbased verification (SVA), and why 100% code coverage still doesn't guarantee a bug-free design Front End vs. Back End Front End — everything from architecture/spec through RTL, verification, and synthesis (logical correctness domain) Back End — everything from a gate-level netlist through to a manufacturable layout (physical implementation domain) Architecture — defining the chip's structure and specification before RTL is written (microarchitecture, block partitioning, interfaces) RTL-to-GDSII flow RTL & Verification → Synthesis (PPA) → Floorplanning / Block Placement → Placement & Route (P&R) → Signoff Floorplanning — deciding where major blocks, macros, and I/O sit on the die before detailed placement Placement & Route — placing standard cells and routing the metal interconnect between them Signoff — the final set of checks a design must pass before tapeout: Static Timing Analysis (STA), Power Integrity (PI) / IR drop / EM (electromigration), DRC (design rule check), LVS (layout vs. schematic) GDSII — the final layout file format sent to the foundry, describing every physical layer/shape on the chip Tool suites (representative, by stage — vendors vary by company/node) RTL/Verification: simulators (e.g., VCS, Xcelium, Questa), formal tools, UVM-based testbenches Synthesis: Design Compiler, Genus Floorplan/Place & Route: Innovus, ICC2 STA: PrimeTime, Tempus Power Integrity / IR-EM: RedHawk, Voltus Physical verification (DRC/LVS): Calibre, PVS Transistor-level circuit simulation (Section 3's analog blocks, and custom PI analysis): SPICE-class simulators (HSPICE, Spectre) What is a PDK? Process Design Kit — the foundry-provided package of design rules, device models, standard cell libraries, and technology files that everything above must target; without a PDK, none of the tools know what the manufacturable silicon actually looks like