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VHDL/Verilog

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Course type: Online Instructor led Course

Platform: Skype

Course ID: 32276

Course type: Online Instructor led Course

Platform: Skype

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Venkateswara Rao picture
Venkateswara Rao

M.Tech VLSI

About Venkateswara Rao

I have 3 years of experience in teaching the VHDL/Verilog. I have been teaching the students since from 2014. I will help the students to do their academic projects.
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About the Course


















































S.NO



VLSI



SESSIONS



1



Introduction to VLSI


Ø  Comparison &impact of different technologies in electronics. (like DSP,ES)


Ø  Real time Application.


Ø   Career in VSLI Domain.



Session 1



2



Project selection.



Session 2,3



3



Course Selection.



Session 4



4



Digital Electronics Review


Ø  IC Design Methodologies


Ø  Combinational ckts &Sequential ckts.


Ø  Realization of gates using MUX’s


Ø  Hazards in Combinational Networks


Ø  Tri –state logic and busses


Ø  Setup and Hold times


Ø  Finite state machines(moore, mealy)


Ø  Analog methodologies


Ø  Digital methodologies


Ø  Examples &assignments


Ø  Memories &Types


Ø  Examples  &Assignments


 



Sessions 5,6,7,8,9



5



VLSI design Flow


Ø  FPGA &ASIC Design cycle



Session 10



6



HDL’s introduction


Ø  Need &Types of HDL


Ø  Advantages with HDL’s



Session 11



7



Introduction to the VHDL Language


Ø  VHDL  Model Components


    Entity Declarations


    Architecture Descriptions


    Timing Model


Ø  Basic VHDL Constructs


    Data Types


    Objects


    Sequential and Concurrent Statements


    Packages and libraries


    Attributes


    Predefined Operators


Ø  Examples


Ø  LAB Section


    



Sessions 12


12


13


14


15


16


17



8



Importance of Test Bench in VlSI Domain


Ø  Overview about Top Module and Test Bench


Ø  Example in VHDL & Lab Session



Session 18















































9



Introduction to Verilog


Ø  Lexical Tokens


Ø  Gate Level Modeling


Ø  Data Types ,Operators and Operands


Ø  Modules Declarations


Ø  Timing Controls


Ø  Examples


Ø  Test Bench



Sessions 19


20


21


22


23



10



Introduction to FPGA


Ø  Outline of FPGA


Ø  Creating a FPGA project


Ø  FPGA schematic Connectivity & Components



Sessions


24


25



11



Review of Project


Ø  Base paper Explanation



Sessions


26,27



12



Project Code Implementation


Output Waveform & Verification


Explanation of Project Blocks for all baches



Sessions


28,29,30



13



Outline of Different HDL TOOLS


Tool Lab session



Sessions 31,32,33



14



Fabrication and Processing Methodologies



Sessions


34,35,36



15



Final Review



Sessions


37,38,39,40



16



A Review on Future Technologies



41



 

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