Avs Bharguav

I hold Masters in Technology from IIT Delhi, where I specialized in optical communication, FPGA-based systems, and digital design, and completed my thesis on encoding and modulation for Visible Light Communication (VLC). Prior to that, I completed an M.Sc. in Physics (Hons.) with Electronics and a B.Sc. in Physics (Hons.), building a strong foundation in electronics, semiconductor devices, and programming. Professionally, I have experience in VLSI and Physical Design, including RTL-to-GDSII implementation, timing analysis, synthesis, and physical implementation using Cadence Genus, Innovus, Virtuoso, and Tempus, along with Verilog and Xilinx Vivado. I currently work as a Product Validation Engineer at Cadence, where I apply my knowledge of semiconductor design flows, debugging, and validation to EDA tools and technologies. My additional strengths include Python, Verilog/RTL design, FPGA development, digital electronics, problem-solving, technical communication, and teaching, and I have also worked as a Teaching Assistant for postgraduate physics laboratory courses.