About the Course
We provide industrial training in Front End VLSI Design by industry expert. Learn real VLSI Design including timing analysis on FPGA Device. Crack all the interview of VLSI Companies.
Topics Covered#Week 1 Front End VLSI Concepts
1. Introduction VLSI Design, Digital System Review 2. Flow of VLSI Design, VLSI Tools & Technologies 3. Finite State Machine and Relevance to VLSI Design 4. Introduction to RTL, Simulation Tools & Techniques 5. Relevance of Timing Analysis.
#Week 2 & 3 RTL Verilog Modeling and Simulation (ModelSim)
1. Overview of Digital Design with Verilog HDL, Hierarchical Modeling Concepts. , Basic Concepts, Modules and Ports. 2. Gate Level Modeling, Data Flow Modeling, Behavioral Modeling. 3. Tasks and Functions 4. Useful Modeling Techniques 5. Advanced Verilog Topics: Timing and Delays, Switch Level Modeling. , User Defined Primitives 6. Programming Language Interface, Logic Synthesis with Verilog HDL
#Week 4 RTL Synthesis
1. Introduction of Synthesis process 2. User Constraints File(Timing and Area parameters) 3. synthesizable constructs 4. Placement and Routing using Floor Planner 5. Timing Analysis 6. Target platform and Logic Mapping 7. Introduction to Xilinx Chip 8. Device Pin Assignment/mapping 7. Device Programming & Verification
Who should attendB.Tech/M.Tech
Pre-requisitesBasics of Digital Electronics
What you need to bringLaptop,notebook,pen"
Key Takeaways1.Student will be able to design projects based on VLSI Front End
2.Expertise on RTL Verilog Modelling & Simulation (Modelsim)
3.Complete knowledge of Synthesis process and implementation on FPGA.