LARA TECHNOLOGY
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LARA TECHNOLOGY

Flat No-301, Flat No.301, VRC Complex, Near Nandi Super Markets, NGO’s Colony, Nandyala, Andrapradesh. N.G.O.S Coloy, Nandyal, India- 518501.

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Overview

We are pleased to introduce ourselves as a trusted organization in providing Software Training Division. JAVA/J2EE , ANDROID, WEB SERVICES, . NET FRAMEWORK, TESTING TOOLS , LOGICAL CODING, BASICS OF C LANGUAGE, SOFT SKILLS, APTITUDE etc. located in Bangalore. We have 9 years of experience in training students in Java/J2EE and project driving stream.
Our course content includes every skill which requires to develop Java/J2ee & .Net related projects.

We are concentrating on every library/ framework/ tool/ server which falls under Java/J2EE development projects.

We have a well stocked data base of our students who undergone Training on Java/J2EE Technologies and we have already provided competent professionals to reputed organizations.

Address

Flat No-301, Flat No.301, VRC Complex, Near Nandi Super Markets, NGO’s Colony, Nandyala, Andrapradesh.

N.G.O.S Coloy, Nandyal, India- 518501.

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LARA TECHNOLOGY conducts classes in .Net AJAX, .Net Training and HTML. It is located in N.G.O.S Coloy, Nandyal. It takes Regular Classes- at the Institute.

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Key Positions Held : 1). Assistant Professor RGMCET, Nandyal 18-12-2000 to 31-06-2006 6 Yrs 7 Months Teaching/Dept. work/ Guiding B.Tech&M, Tech students projects /Planning for labs evelopment/labs Establishment 2). Associate Professor RGMCET, Nandyal 01-07-2006 to 31-10-2006 4 Months Teaching/Dept. work/ Guiding B.Tech&M, Tech students projects 3). JTO, BSNL, Shimla dist. BSNL, Shimla dist. 01-12-2006 to 09-07-2007 7 Months JTO Training Phase-1/Telecom Indoor work 4). Associate Professor RGMCET, Nandyal 15-07-2007 to 31-10-2013 6 Yrs 3 months Teaching/Dept. work/ Planning for labs development/ Guiding B.Tech&M, Tech students projects /labs Establishment 5). Professor RGMCET, Nandyal 31-10-2013 to till date 1 Yr up to now Teaching/Dept. work/ Research & Development/Guiding B.Tech&M, Tech students projects /labs Establishment Invited Talks: i) Delivered a presentation on Low power VLSI design using Microwind 3.1 tool at the workshop conducted by ECE Dept. in RGMCET, Nandyal, in 31-05-2011. ii) Delivered a visiting Lecture in EMTL subject in Anurag College of Engg., Hyderabad in 2011. iii) Delivered a visiting Lecture in LICA subject in AVR&SVR Engg. College, Kurnool in 2012. iv) Delivered a visiting Lecture in EMTL subject in AVR&SVR Engg. College, Kurnool in 2012. Research Outputs: 1. Books / Monograms: Published a book titled “Design of High Performance CMOS circuits using Domino Logic” by Scholar’s Press, Deutschland, Germany with ISBN: 978-3-639-71281-0 in 2014. 2. Articles in Journals & Conferences : Total Published : 39 International Journals : 24 National Journals : 1 International Conferences : 7 National Conferences :7 International Journals Published: 1. S.Govindarajulu and Dr.T.J.C.Prasad “Low Power, Energy-efficient Domino Logic Circuits” , International Journal of Recent Trends in Engineering , Vol 2, No.7, November 2009, Academy Press, pp30-33, ACEEE, Finland.SEARCH Digital library, SearchDl ID: 01.IJRTET.2.7.196 2. S.Govindarajulu and Dr.T.J.C.Prasad “Temperature Variation Insensitive Energy-Efficient CMOS Circuit Design in 65nm Technology” , International Journal of Engineering Science and Technology, Vol 2(6), 2010, pp2140-2147, ISSN:0975-5462.Open Access Indexed, ICV factor:3.14, ISO 3297:2007, Sci Rate indexed. 3. S.Govindarajulu and Dr.T.J.C.Prasad “Energy-Efficient Reduced Swing Domino Logic Circuit in 65nm Technology”, International Journal of Engineering Science and Technology, Vol 2(6), 2010, pp2248-2257, ISSN:0975-5462. Open Access Indexed, ICV factor:3.14, ISO 3297:2007 4. S.Govindarajulu and Dr.T.J.C.Prasad “ Design of Low Power, High Speed, Dual Threshold Voltage CMOS Domino Logic Circuits with PVT Variations”, International Journal of Electronic Engineering Research, Vol 2, Number 5, 2010, pp619-629, ISSN:0975-6450.Research India Publications journal. 5. S.Govindarajulu and Dr.T.J.C.Prasad “High Performance VLSI Design Using Body Biasing in Domino Logic Circuits”, International Journal on Computer Science and Engineering, Vol.2, No.05, 2010, , pp1741-1745, ISSN:0975-3397.Sci Rate indexed, Scirus indexed, Copernicus indexed. 6. S.Govindarajulu and Dr.T.J.C.Prasad “Design of High Performance Dynamic CMOS Circuits in Deep Submicron Technology”, International Journal of Engineering Science and Technology, Vol 2(7), 2010, pp2903-2917, ISSN:0975-5462.Open Access Indexed, ICV factor:3.14, ISO 3297:2007, Sci Rate indexed. 7. S.Govindarajulu and Dr.T.J.C.Prasad “Design of energy-efficient Dual- VtDomino Logic Circuits in 65 nm Technology”, International Journal of Advances in Science and Technology, Vol 1 , No.3, 2010, pp56-62, ISSN:2229-5216.British &Europian library Indexed. 8. S.Govindarajulu and Dr.T.J.C.Prasad “Robust, Energy-Efficient Reduced Swing Domino Logic Circuits”, International Journal of Recent Trends in Engineering and Technology, Vol.3, No.4, May 2010, pp130-134, ACEEE, Finland.SearchDl ID: 01.IJRTET.3.4.73 9. S.Govindarajulu and Dr.T.J.C.Prasad “Performance Design metrics for CMOS Designs in DSM Technology”, International Journal of Advances in Science and Technology , Vol.2, No.3, March 2011, pp71-88, ISSN:2229-5216.British &Europian library Indexed. 10. S.Govindarajulu and Dr.T.J.C.Prasad “Design of High performance arithmetic and logic circuits in DSM Technology”, International Journal of Engineering and Technology , Vol.2, No.4, 2010, pp285-291, ISSN:0975-4024, SCOPUS Indexed. 11. S.Govindarajulu and Dr.T.J.C.Prasad et.al “Energy-efficient, domino VLSI circuits and their performance with PVT variations in DSM Technology”, International Journal of Advanced Engineering Sciences and Technologies , Vol.5, No.2, 2011, pp319-337, ISSN:2230-7818.ICV:5.09, IEI Indexed. 12. S.Govindarajulu and Dr.T.J.C.Prasad et.al “Energy-efficient, noise-immune CMOS domino VLSI circuits in VDSM Technology”, International Journal of Advanced Computer Science and Applications, Vol.2, No.4, 2011, pp105-116, ISSN:2158-107X, The SAI Publishers, USA.IET Inspec Direct indexed.Impact factor:1.34 13. S.Govindarajulu and et.al “Design of Energy-efficient, High performance CMOS flip-flops in 65 & 120 nmTechnology”, International Journal of Advances in Science and Technology , Vol.2, No.3, March 2011, pp44-54, ISSN:2229-5216. 14. S.Govindarajulu and Dr.T.J.C.Prasad et.al “Multilayer AHB Bus matrix with self motivated arbitration scheme”, International Journal of Advances in Science and Technology , Vol.2, No.3, March 2011, pp9-17, ISSN:2229-5216.British &Europian library Indexed. 15. S.Govindarajulu and et.al “An efficient keeper technique for dynamic logic circuits”, International Journal of Science and Advanced Technology , Vol.2, No.5, May 2012, pp34-38, ISSN:2221-8386.Sci Rate indexed, Copernicus Indexed. 16. S.Govindarajulu and et.al “Novel keeper technique for Domino logic circuits in DSM Technology”, International Journal of Latest Research in Science and Technology , Vol.1, No.2, July-August, 2012, pp127-131, ISSN:2278-5299, Copernicus Indexed, JournalIF:1.979. 17. S.Govindarajulu and et.al “Image registration on satellite images”, IOSR Journal of Electronics and communication engg., Vol.3, Issue No.X, September-October, 2012, pp1-8, ISSN:2278-2834.Impact Factor (African Quality Centre for Journals)AQCJ:1.586 18. S.Govindarajulu and et.al “A Comparison of SIFT, PCA-SIFT and SURF”, International journal of Innovative in Engg. & Research, Vol.6, Issue No.1, December, 2012, pp 53-60, ISSN:2319-5665. 19. S.Govindarajulu and et.al “Novel Low power and high speed array divider in 65 nm Technology”, International Journal of Advances in Science and Technology , Vol.6, No.6, March 2013, pp44-56, ISSN:2229-5216.British &Europian library Indexed. 20. S.Govindarajulu and et.al “Circuit optimization for Transmission gate Master Slave flip-flops”, International Journal of Computers and Technology, Vol.11, No.3, October 2013, pp2387-2392, ISSN:2277-3061, Impact factor:1.532. 21. S.Govindarajulu and et.al “Performance of full adders with analyzation of logic and circuit implementation”, International Journal of Electronics and Data Communication, Vol.3, No.4, December 2013, pp 47-54, ISSN:2278-5620.Impact factor:0.637 22. S.Govindarajulu and et.al “Design of Energy-efficient and High performance VLSI adders”, International Journal of Engineering Research, Vol.3, Special Issue 2, March, 2014, pp.55-59, ISSN: 2319-6890)(online), 2347-5013(print), ISI (Thomson Reuters)Impact factor:0.732, Impact Factor(Research Bib) : 5.49 23. S.Govindarajulu and et.al “Low leakage bit-line SRAM Design architectures”, International Journal of Engineering Research, Vol.3, Special Issue 2, March, 2014, pp.81-87, ISSN: 2319-6890)(online), 2347-5013(print), ISI (Thomson Reuters)Impact factor:0.732, Impact Factor(Research Bib) : 5.49 24. S.Govindarajulu and et.al “Switching DC-DC converters with hybrid control schemes”, International Journal of Engineering Research, Vol.3, Special Issue 2, March, 2014, pp.116-120, ISSN: 2319-6890)(online), 2347-5013(print), ISI (Thomson Reuters)Impact factor:0.732, Impact Factor(Research Bib) : 5.49 National Journals 1. S.Govindarajulu, Dr.T.Jayachandra Prasad et.al. “Low Power, Reduced Dynamic Voltage Swing Domino Logic Circuits” Indian Journal of Computer Science and Engineering, Vol.1, No.2, 2010 pp.74-81, ISSN:0976-5166. Conference Contributions : International Conferences 1. S.Govindarajulu and Dr.T.J.C.Prasad “Consideration of performance Factors in CMOS Designs” ICED2008 International conference on Electronic design 1st-3rd December, 2008 at Penang, Malaysia, IEEE, Xplore 2. S.Govindarajulu and Dr.T.J.C.Prasad “Low-Power, High Performance Dual Threshold Voltage CMOS Domino Logic Circuits” International Conference on Recent Advancements in Electrical Sciences(ICRAES’10)8th and 9th jan’2010, Organized by Dept of EEE and ECE, KSR College of Engineering, Tiruchengode, Tamil Nadu, India, vol.III, No.1, pp109-118. 3. S.Govindarajulu and Dr.T.J.C.Prasad et.al “Temperature Variation Insensitive Energy – Efficient CMOS Circuits design in DSM Technology” Ist International Conference on Emerging Trenfs in Signal Processing and VLSI Design , 11th and 13th June’2010, Organized by Dept of ECE, Guru Nanak Institutions (Guru Nanak Institutions Professional Activities), Hyderabad , Andhra Pradesh, India, pp1179-1183. 4. S.Govindarajulu and Dr.T.J.C.Prasad et.al “Energy –efficient Low Voltage Swing Domino Logic Circuits in DSM Technology” Ist International Conference on Emerging Trenfs in Signal Processing and VLSI Design , 11th and 13th June’2010, Organized by Dept of ECE, Guru Nanak Institutions (Guru Nanak Institutions Professional Activities), Hyderabad , Andhra Pradesh, India, pp946-951. National Conferences 1. S.Govindarajulu and Dr.T.J.C.Prasad “Runtime Leakage Power Reduction Techniques in DSM Technology:A Review” Second National Conference on Communication technologies(NCCT’08), D


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