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IdentityI have recently completed my B.E. in Electronics and Communication Engineering and have hands-on experience in RTL Design and Verification using Verilog, SystemVerilog, and UVM. I have worked on AMBA protocols (AXI, AHB, APB) and have 6 months of internship experience at Smart DV Technologies, now 5th running. where I developed and verified protocol-based test benches. and designed APB2AHB Bridge. now present role in intern also IP.
I am also currently building my knowledge in Design for Testability (DFT), including scan chains and ATPG.
Boduppal Mallika Arjun Nagar, Hyderabad 
Certified
