Mohanapriya R.

I am currently pursuing my PhD in VLSI Design at VIT Vellore, focusing on hardware implementation of lightweight cryptographic algorithms for IoT security. My research involves designing compact, low‑power S‑boxes and block ciphers (like PRESENT, SIMON, SPECK) and implementing them efficiently on FPGA and ASIC platforms. I also work on VLSI‑based image encryption schemes, combining chaotic maps with lightweight crypto to secure multimedia data in resource‑constrained devices.I have published several papers in IEEE and Elsevier journals on topics such as low‑area S‑box architectures, side‑channel resistant implementations, and hardware‑oriented image encryption. I use Verilog/SystemVerilog for RTL design, Synopsys and Cadence tools for synthesis and timing analysis, and Xilinx Vivado for FPGA prototyping. My work aims to bridge the gap between strong cryptographic security and the strict power/area constraints of IoT and edge devices.