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Final year project

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Kadubeesanahalli, Bangalore

Course ID: 41895

Kadubeesanahalli, Bangalore

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About the Course

This course is for students who want to do projects in VLSI domain keeping semiconductor industry in mind. I will provide basic classes on System Verilog, Verilog and then help selecting B.Tech projects in Front-end/Functional Verification of IP (Intellectual propetry) using System verilog and Verilog.

This course is must for students who are looking forward to pursue career in VLSI/Semiconductor domain. It is also helpful for FInal year grads to get pre-industry experience and would enable them to face interviews confidently

Course run on weekends i.e. Saturdays and Sundays morning session. 3.5 hours each day for 3 weeks. First 2 sessions help basics and essentials of System verilog and Verilog and Next 2 sessins in understanding spec and coding guidelines and final 2 sessions in completing the project

Post course support would be provided if needed. 

Projects would be taken in accordance with Industry practices i.e. Deside on Design to be verified. Understand the spec. Come up with the test plan. Decide on verification strategy. Develop infrastructure. Write test cases and then work on coverage goal closure. Also, help is provided to debug failures observed during simulations or any issue faced while writing verification test bench.

Looking forwards to conduct first class with you. 

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About the Trainer

Prankul Agarwal picture

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2 Courses

Prankul Agarwal

B.Tech/Mtech Electrical Engg from IIT Madras

5 Years of Experience

8 years experience in Hardware design and verification.


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Students Interested 0 (Seats Left 0)

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