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Digital Design using Verilog

HSR Layout, Bangalore


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1 Interested

About the Course

Complete verilog classes and labs are online

Topics Covered

Introduction to Verilog
• What is Verilog?
• Scope of Verilog
• Design flow
• Verilog-2001

Verilog Basics
• Modules & ports
• Continuous assignments
• Comments
• Names
• Nets and strengths
• Design hierarchy
• Module instances
• Primitive instances
• Text fixtures
• $monitor
• Initial blocks
• Logic values
• Vectors
• Registers
• Numbers
• Output formatting
• Timescales
• Always blocks
• $stop and $finish
• Using nets and variables correctly

Combinational Logic
• Event control
• If statements
• Begin-endw Incomplete assignment and latches
• Unknown and don’t care
• Conditional operator
• Tristates
• Case, casez and casex statements
• full_case and parellel_case directives
• For, repeat, while and forever loops
• integers
• Self-disabling blocks
• Combinational logic synthesis

Sequential Logic
• Synthesising flip-flops & latches
• Avoiding simulation race hazards
• Nonblocking assignments
• Asynchronous & synchronous resets
• Clock enables
• Synthesizable always templates
• Designing state machines
• State machine architectures
• Verilog code-based FSM strategy
• State encoding
• Unreachable states & safe design practices
• One-hot machines

Other features of Verilog
• Verilog operators
• Part selects
• Concatenation & replication
• Shift registers
• Conditional compilation
• Parameterisation and generate
• Hierarchical names
• Arithmetic operators and their synthesis
• Signed and unsigned values
• Memory arrays
• RAM modelling and synthesis
• $readmemb and $readmemh

Finite State Machines (FSMs)
• Review of Moore and Mealy state machines
• Finite state machines representation
• Use of enums to represent state
• FSM code structure
• FSM implementation example
• Synthesis of FSMs

Tasks and Functions
Subprograms and Packages
• Understanding tasks
• Task arguments
• Task synchronization
• Tasks and synthesis
• Functions

Test Fixtures
• File I/O – Writing to files,Reading from files
• Automated design verification using Verilog
• Force and release

Behavioural Verilog
• Algorithmic coding
• Synchronization using waits & event control
• Concurrent-disabling of always blocks
• Named events
• Fork & join
• Understanding intra-assignment controls
• Blocking and nonblocking assignments
• Continuous procedural assignment

Gate Level Verilog
• Structural Verilog
• Using built-in primitives
• Net types & drive strengths
• net & path delays
• Specify blocks

Who should attend

B-Tech or M-Tech students, People who are looking for job in VLSI core companies, Freshers etc


Basic digital electronics

What you need to bring

LAPTOP / pC with internet connection

Key Takeaways

Docs and materials , lab materials
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About the Trainer


B-Tech with working experience in industry

More than 1 year of industry experience
Seats Left-

Students Interested 1

Course Id: 26677