Signup as a Tutor

As a tutor you can connect with more than a million students and grow your network.

Digital Design using Verilog

No Reviews Yet

HSR Layout, Bangalore

Course ID: 26677

HSR Layout, Bangalore

Students Interested 1 (Seats Left 0)

No Reviews Yet

About the Course

Complete verilog classes and labs are online

Topics Covered

Introduction to Verilog
• What is Verilog?
• Scope of Verilog
• Design flow
• Verilog-2001

Verilog Basics
• Modules & ports
• Continuous assignments
• Comments
• Names
• Nets and strengths
• Design hierarchy
• Module instances
• Primitive instances
• Text fixtures
• $monitor
• Initial blocks
• Logic values
• Vectors
• Registers
• Numbers
• Output formatting
• Timescales
• Always blocks
• $stop and $finish
• Using nets and variables correctly

Combinational Logic
• Event control
• If statements
• Begin-endw Incomplete assignment and latches
• Unknown and don’t care
• Conditional operator
• Tristates
• Case, casez and casex statements
• full_case and parellel_case directives
• For, repeat, while and forever loops
• integers
• Self-disabling blocks
• Combinational logic synthesis

Sequential Logic
• Synthesising flip-flops & latches
• Avoiding simulation race hazards
• Nonblocking assignments
• Asynchronous & synchronous resets
• Clock enables
• Synthesizable always templates
• Designing state machines
• State machine architectures
• Verilog code-based FSM strategy
• State encoding
• Unreachable states & safe design practices
• One-hot machines

Other features of Verilog
• Verilog operators
• Part selects
• Concatenation & replication
• Shift registers
• Conditional compilation
• Parameterisation and generate
• Hierarchical names
• Arithmetic operators and their synthesis
• Signed and unsigned values
• Memory arrays
• RAM modelling and synthesis
• $readmemb and $readmemh

Finite State Machines (FSMs)
• Review of Moore and Mealy state machines
• Finite state machines representation
• Use of enums to represent state
• FSM code structure
• FSM implementation example
• Synthesis of FSMs

Tasks and Functions
Subprograms and Packages
• Understanding tasks
• Task arguments
• Task synchronization
• Tasks and synthesis
• Functions

Test Fixtures
• File I/O – Writing to files,Reading from files
• Automated design verification using Verilog
• Force and release

Behavioural Verilog
• Algorithmic coding
• Synchronization using waits & event control
• Concurrent-disabling of always blocks
• Named events
• Fork & join
• Understanding intra-assignment controls
• Blocking and nonblocking assignments
• Continuous procedural assignment

Gate Level Verilog
• Structural Verilog
• Using built-in primitives
• Net types & drive strengths
• net & path delays
• Specify blocks

Who should attend

B-Tech or M-Tech students, People who are looking for job in VLSI core companies, Freshers etc

Pre-requisites

Basic digital electronics

What you need to bring

LAPTOP / pC with internet connection

Key Takeaways

Docs and materials , lab materials

Date and Time

Not decided yet.

About the Trainer

Avg Rating

Reviews

Students

Courses

Nuzrath

B-Tech with working experience in industry

More than 1 year of industry experience

Reviews

No reviews currently

Discussions

Students Interested 1 (Seats Left 0)

Post your requirement and let us connect you with best possible matches for Embedded & VLSI Classes Post your requirement now

UrbanPro.com is India's largest network of most trusted tutors and institutes. Over 25 lakh students rely on UrbanPro.com, to fulfill their learning requirements across 1,000+ categories. Using UrbanPro.com, parents, and students can compare multiple Tutors and Institutes and choose the one that best suits their requirements. More than 6.5 lakh verified Tutors and Institutes are helping millions of students every day and growing their tutoring business on UrbanPro.com. Whether you are looking for a tutor to learn mathematics, a German language trainer to brush up your German language skills or an institute to upgrade your IT skills, we have got the best selection of Tutors and Training Institutes for you. Read more