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Certificate Course in VLSI Verification

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Yeshwanthpur, Bangalore

Course ID: 14603

Yeshwanthpur, Bangalore

Students Interested 3 (Seats Left 0)

No Reviews Yet

About the Course

This course aims at providing detailed knowledge in VLSI Verification process. This course covers Digital Design, Hardware descriptive languages verification
using system verilog, and UVM Methodology along with Project implementation. Going through the course will help learners to understand the entire Logic and ASIC Verification process and become equipped to take on the challenges posed by the ever demanding chip design.

Topics Covered

Module 1: Digital Design:
Introduction to VLSI Design Flow, Numbers systems, Boolean Algebra, Minimization,
Combinational circuits, Sequential circuits, Finite State Machines & Digital Circuit
Design for Practical Applications.

Module 2: Verilog HDL:
Introduction to Verilog, Language Concepts, Data types, Gate level Modeling, Data
Flow Modeling, Behavioral Modeling, Test benches, Tasks and Functions, System
tasks and Files & Advanced Verilog Constructs.

Module 3: Design Verification:
Introduction to verification, verification cycle, Different types of test benches,
Verification Tools, Stimulus and Response, Introduction to BFMs, Verification
environment and its components, Introduction to Verification Plan & Code coverage.
Project – Industry Standard

Module 4: System Verilog (HVL)
Data types and operators, Procedural Blocks, Inter Process Communication(IPC),
Tasks & Functions, Class and Objects, Constraint Random Verification (CRV),
Interface, Mailbox, Functional coverage & Verification Environment.
Project – Industry Standard.

Module 6: UVM
Introduction to UVM, UVM Factory, UVM Test-bench Phases and components, Agent
and its components, Sequences, Driver, TLM Modeling, Agent Monitor, Checker &
Score Board.

Module 5: Static Timing Analysis
Concept of static timing analysis, Timing constraints, Timing models, Critical Path
Analysis, False Path Analysis & Dynamic timing verification

Module 7: System level verification and re-usability:
Re-usability, Components, System Level Test-bench, Coding for UVM based
Verification, Emulation & Co-Simulation.
Module 8: Formal Verification
Need for Formal Verification, SV assertions, Property, Scripting for Formal Verification
& Verifying a Simple IP.

Module 9: Project - Industry Standard:
Based on the knowledge gained, and with the help of various tools, all the participants
will have to develop a project with complete design and verification flow.

Who should attend

BE / B.Tech (ECE / EEE / EIE), ME / M.Tech (ECE/ EEE / EIE) or M.Sc. Electronics


Should have knowledge on Digital Electronics basics,

What you need to bring


Key Takeaways

The course will help learners to understand the entire Logic and ASIC Verification process and become equipped to take on the challenges posed by the ever demanding chip design.

Date and Time

Not decided yet.

About the Trainer

Avg Rating

0 Reviews

0 Students

4 Courses

Mr. Shaik

Post Graduation

8+ years of Industry experience.


No reviews currently Be the First to Review


Students Interested 3 (Seats Left 0)

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