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Indian Institute Of Technology, Chennai

Course ID: 24545

Indian Institute Of Technology, Chennai

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Date and Time

Not decided yet.

About Seetal Potluri

I am a PhD graduate from Electrical Engineering department at IIT Madras. I have pursued PhD with an explicit motivation to contribute towards teaching. I have presented papers in top-tier IEEE conferences like DAC, ICCD and ETS. I have been partaking teaching at undergraduate as well as graduate levels in IIT for the past 4 years.
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About the Course

Dear Student,

Welcome to the world of digital electronics!

Most of modern digital chips are made of metal oxide semiconductor (MOS) transistors. Due to Moore's scaling, very large scale integration (VLSI) has become a reality today. As a result, it has become possible to design multi-billion transistor digital chips, offering several teraflops of performance throughput. Clearly it is infeasible to design these large chips completely through manual efforts. So, there was a dire need for computer-assisted automatic design of these large digital chips with minimal manual intervention.

Interestingly, MOS based digital design is highly noise-tolerant, making itself amenable to large scale automation. In this course, we will discuss how designers use circuit theory, graph theory, boolean logic and several other powerful mathematical tools to exploit this property to efficiently design large digital chips. Additionally, we will also see how timing, area and power are the primary metrics governing digital VLSI design. Standard design practices that aim at optimizing these parameters and how different phases of the VLSI flow address these issues, will be discussed in detail.

We will begin with combinational circuits, and after attaining a sufficient comfort level with the same, we will move to the design of sequential circuits. The timing issues relating to sequential circuits is a topic unto itself. We will discuss set-up time, hold-time, clock-skew, clock-Q delay, wire delay and all the parameters governing timing in MOS based sequential circuits. We will see how testing of sequential circuits is very hard, and how this problem is solved by the industry 25 years ago using the scan architecture. We will also discuss formal verification technique for both combinational and sequential circuits.

I strongly encourage students with CSE, ECE and EEE backgrounds, who are looking to kickstart a career in VLSI, and who have some interest in programming, to take this course. Many contemporary VLSI courses focus on using the tools. On the contrary, we will focus on building the tools. This course will contain programming assignments, making the student understand the computational issues faced by a VLSI designer. The progamming part is a key part of this course, which will help the students appreciate the Design Automation better.

Overall, this course will start you at the beginner level and will take you to the expert level. I am sure you will enjoy the course, provided you are enthusiastic and put in good time in doing the assignments. All the best!


Topics Covered

MOS based NOT gate

MOS transistor networks to realize complex gates

Logic synthesis and High level synthesis

Physical synthesis

Area, Timing and Power analysis treating combinational circuit as a directed acyclic graph

Sequential circuits and scan based sequential circuit design

Area, Timing and Power analysis of sequential circuits

Formal Verfication of combinational and sequential circuits

Testing of combinational and sequential circuits

Who should attend

Preferably students from ECE, CSE and EEE backgrounds.


Preferably the student should have taken the following courses
1. Digital Logic
2. Circuit Design
3. Data Structures and Algorithms
3. C/C++/Perl Programming

What you need to bring

Notebook, pen and a laptop (with linux installed on it).

Key Takeaways

Students will learn
1. MOS based digital design
2. Digital VLSI flow
3. Building tools for various phases of the VLSI flow


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